Former Intel CEO Pat Gelsinger sees hardware renaissance in memory, optical interconnects

Gelsinger's thesis exposes a structural mispricing: AI is compressing chip design costs toward zero, but physics doesn't negotiate. When a five-person team ships in six months what once took two hundred engineers two years, the value pool migrates from "writing code" to "building atoms" — manufacturing precision, thermal management, interconnect bandwidth, and energy efficiency are redefining who captures margin in the semiconductor stack. Optical interconnects are the most underappreciated link. Copper's loss tangent hits a hard wall above 200 GHz, while AI cluster scale-out bandwidth compounds at 3-4x annually. Within 18 months, co-packaged optics shifts from roadmap to standard BOM line item, and InP laser plus silicon-photonics engine capacity becomes the new "EUV lithography" — the binding constraint no one is pricing in. On memory, HBM4's 3D stacking forces DRAM makers to renegotiate capacity with advanced packaging houses. The SK Hynix-Samsung contest escalates from "who ships first" to "who controls yield on opto-electronic-memory integrated packaging." The real chokepoint isn't technical — it's energy. Once a single GPU's TDP crosses 1,000W, the bottleneck migrates from the die to the transformer and coolant loop. Power infrastructure, not the fab, becomes the next geopolitical flashpoint.