Exclusive Interview: Inside VSMC's Singapore fab, where silicon interposers and power chips underpin AI growth

While TSMC refrained from building its own fab in Singapore, its strategic backing of VSMC for silicon interposers and power ICs effectively outsources geopolitical risk into a third-party foundry model. This move intensifies AI packaging’s reliance on advanced substrates, compelling OSATs like ASE and Amkor to fast-track hybrid bonding integration. TSMC’s massive U.S. capex—where 300mm wafer costs run ~40% above East Asia—reveals a defensive play against export controls, using joint ventures as regulatory shields. In response, Samsung may deepen its power-device collaboration with GlobalFoundries in Singapore, while Intel could accelerate divestitures of non-core packaging units to concentrate on Co-EMIB. Over the next 18 months, Southeast Asia will serve as a gray-zone buffer for competing tech standards; however, without EUV scaling rights, VSMC’s >28nm capacity risks structural oversupply by 2027.