Everspin demos CXL-connected MRAM memory expansion - Blocks & Files

The CXL+MRAM pairing is not a product demo—it is a structural insertion of a persistent hot tier between DRAM and NVMe, rewriting the memory BOM of AI inference servers. Everspin's choice of IP licensing over wafer sales signals intent to own the reference-design entry point for MRAM-on-CXL, echoing Qualcomm's baseband-IP playbook a decade ago. It sells architecture leverage, not silicon. Ripple effects run in two directions. Upstream, the joint validation window between CXL controllers (Marvell, Astera) and SOT-MRAM cell designs compresses, shifting pricing power on 12/14nm MRAM lines toward IP holders. Downstream, once KV-cache workloads migrate to the CXL-MRAM layer, DRAM's share of server BOM could drop from roughly 40% to 25%, forcing Micron and Rambus to redraw their CXL roadmaps. On competition: Samsung and SK Hynix hold dual DRAM+MRAM stacks, but CXL governance sits with Intel and AMD. Everspin's 12-to-24-month litmus test is whether CXL 3.1 memory-pooling clauses receive native KVM/VMware support and whether it lands at least one hyperscaler pilot. If both hit, MRAM graduates from niche storage to a third memory tier. Risk vector: CXL Consortium governance is US-centric. If export controls extend to CXL controller ASICs, packaging in Taiwan, China and cloud procurement on the mainland face disruption. Everspin, as a pure US IP house, paradoxically benefits near-term from de-risking procurement preferences.