Ennostar's optical push could add new growth engine for 2027 and onward

Ennostar's pivot into Micro VCSEL isn't a product-line expansion—it's a structural grab for the optical-packaging chokepoint in CPO architecture. The real bottleneck in co-packaged optics isn't the laser diode; it's millimeter-scale thermal-electrical-optical co-integration between the optical engine and switch ASIC. That's precisely where Ennostar's advanced-packaging DNA becomes a moat. Upstream, InP epitaxial wafer capacity (Sumitomo, JX Metals) will be the hidden constraint through 2027. Downstream, Broadcom's Tomahawk and Marvell's Teralynx optical-engine interfaces face forced redesign as CPO displaces pluggable transceivers. Supply-chain exposure is acute: InP substrates remain concentrated in Taiwan, China and Japan, while tightening US export controls on advanced optical components raise compliance costs for any design-win with North American hyperscalers. If CPO becomes the de facto standard, optical-engine packaging IP will be the next trade-restriction flashpoint. Competitively, Coherent and Lumentum threaten at the chip level, but Ennostar's play is packaging-as-barrier—the TSMC analogy. Whoever owns 2.5D/3D optical-engine integration locks in hyperscaler architecture choices. Once a design-in is locked, switching costs are prohibitive. The 2025-2026 sample-validation window is therefore worth more than the 2027 revenue line. The 12-24 month tail: 1.6T switch-ASIC ramp timing sets the CPO adoption curve. Ennostar's real bet is landing in two or more hyperscaler reference designs before that window closes.