Energy use forcing rethink of AI chip design, TSMC says - The Economic Times

The soaring electricity demands of artificial intelligence are reshaping chip design priorities, with energy efficiency now taking precedence over raw computing power. TSMC's senior executive Kevin Zh... Read original →

Soaring AI power demands are triggering a paradigm shift in chip architecture. TSMC’s (Taiwan, China) delay of High-NA EUV adoption signals that energy efficiency now trumps transistor scaling—3D stacking and advanced packaging have evolved from performance enhancers to system-level necessities. Upstream, ASML faces strategic reassessment; downstream, cloud giants like Google and Meta will accelerate Chiplet-based custom designs to slash datacenter PUE. U.S. EUV export controls inadvertently spurred Huawei’s Tau Scaling Law, optimizing on-chip data movement—a stopgap today but potentially a non-von Neumann breakthrough tomorrow. Within 18 months, performance-per-watt will dictate AI chip pricing. NVIDIA and AMD risk losing training market share to hyperscaler-custom ASICs if they cling to general-purpose GPU roadmaps. Geopolitical competition has escalated from equipment bans to a battle over the very definition of efficiency in the AI stack.