Energy use forcing rethink of AI chip design, TSMC says - ET Telecom

TSMC's recent statement highlights how escalating energy consumption issues are compelling the entire AI chip design industry to reassess and adjust technical approaches. As artificial intelligence ap... Read original →

TSMC’s (Taiwan, China) warning on AI chip power constraints is a stress test for the entire semiconductor ecosystem. Technically, pushing transistor density beyond 3nm with EUV alone hits thermal and power walls, forcing co-optimization across EDA, advanced packaging (e.g., CoWoS), and HBM architectures. Regulatory risks are mounting: the EU Chips Act and U.S. Inflation Reduction Act impose strict green manufacturing thresholds, potentially excluding high-energy fabs from subsidies or imposing carbon tariffs. NVIDIA, AMD, and Intel will accelerate chiplet and near-memory computing to bypass monolithic power ceilings, while Samsung may leverage GAA transistors to capture low-power AI inference. Within 18 months, performance-per-watt—not peak TOPS—will dominate procurement decisions, shifting the industry from raw compute races to energy-aware design. Foundries without credible low-carbon roadmaps face existential marginalization.