Energy use forcing rethink of AI chip design, TSMC says - CNA

A senior TSMC executive stated that rising electricity demands from AI applications are shifting chip design priorities toward energy efficiency rather than raw computing power. This trend is reshapin... Read original →

The AI power wall is triggering a paradigm shift from peak performance to energy efficiency—a strategic pivot, not just a technical tweak. TSMC’s deliberate slowdown in next-gen EUV adoption and intensified focus on 3D stacking and photonics reflect a pragmatic retreat from Moore’s Law under U.S.-led tech restrictions. Huawei’s ‘Tau Scaling Law’ exemplifies how rivals are decoupling performance gains from EUV dependency, eroding the sole advantage of leading-edge nodes. This reshapes the entire stack: ASML faces surging demand for heterogeneous integration tools, while cloud titans like Microsoft and Meta prioritize custom, low-wattage AI accelerators to cap soaring electricity bills. Within 12–24 months, performance-per-watt will dictate chip valuations, penalizing firms over-invested in sub-7nm scaling. Despite Taiwan, China’s current manufacturing dominance, its foundry leadership hinges on mastering system-level innovation beyond lithography—failure here risks irreversible erosion by 2027.