Energy efficiency becoming most important chip design consideration, TSMC executive says - marketscreener.com

A TSMC executive recently stated that energy efficiency has become the most critical consideration in chip design, reflecting new challenges and opportunities facing the entire semiconductor industry.... Read original →

TSMC’s (Taiwan, China) declaration that energy efficiency now dominates chip design signals a structural pivot from performance-centric to power-aware engineering. Technologically, its 3nm and beyond nodes are forcing EDA vendors, IP developers, and packaging innovators to co-optimize for ultra-low leakage—accelerating Chiplet adoption in data centers. Regulatory pressure is intensifying: the EU Green Deal and U.S. Inflation Reduction Act impose strict carbon accounting, making high-power chips vulnerable to trade barriers unless backed by certified green manufacturing. Competitors like Samsung and Intel will likely subsidize early access to their sub-2nm low-power processes to lure AI clients, yet lag in yield maturity and ecosystem depth. Within 18 months, energy efficiency—not raw TOPS—will become the decisive metric for AI accelerator selection, pushing the entire supply chain toward near-threshold computing and heterogeneous integration. Laggards risk exclusion from premium markets.