electronica: Infineon's Seriously SiC 300-mm Wafer on Display - Electronic Design

Infineon's 300mm SiC wafer at electronica is not a product demo—it is a structural cost-reset signal for the entire power semiconductor chain. The real leverage is not the larger diameter but the BOM math: SiC substrates consume 40-50% of device cost, and doubling wafer area slashes per-die cost by nearly half. More critically, Infineon can reuse its mature 300mm silicon back-end equipment—lithography, CMP, metallization—at Dresden and beyond. That capex synergy is something Wolfspeed and STMicroelectronics cannot replicate on their 150mm/200mm lines. On the regulatory front, the EU Chips Act is forcing supply-chain decoupling. By showcasing 300mm now, Infineon is filing a strategic-autonomy declaration with Brussels, severing the fragile Chinese-substrate-plus-European-device dependency. Competitively, Wolfspeed's financial distress opens a window. ST's Tesla 800V partnership offers a short-term moat, but once 300mm yields stabilize in 2026-2027, ST's 150mm lines become a cost liability. Rohm and Mitsubishi will follow, yet Japan lags two generations in SiC substrate yield. Over the next 12-24 months, AI data-center 800V architectures and EV demand will push SiC from niche to commodity. Infineon's 300mm is the opening move in a pricing-power war. Whoever cracks mass-production yield first anchors the power semiconductor price curve for the next five years.