Document shows TSMC could use as much energy as 300,000 homes - KJZZ

The "300,000 homes" figure is not a sustainability footnote—it is a structural signal that energy infrastructure, not lithography, is becoming the binding constraint on sub-3nm scaling. Each node shrink below 3nm raises per-wafer energy density by 15-20%, a thermodynamic floor no engineering iteration can erase. The cascade is already visible: transformer lead times in Arizona stretch to 24 months; Taiwan, China's grid capacity is a harder bottleneck than ASML's EUV output. Siemens and Hitachi order books extend past 2027. On compliance, if the EU's CBAM extends to semiconductors, TSMC's per-wafer embedded carbon cost rises 8-12%. More critically, NVIDIA and Apple now weight supplier carbon intensity in procurement—energy data is migrating from ESG appendix to P&L line item. Competitively, Samsung and Intel face a non-technical variable in the 2nm race: the energy-efficiency narrative. If TSMC embeds "transistors per joule" into investor communications, it builds a second moat beyond yield. 12-24 month outlook: fab siting logic shifts from "proximity to customers" to "proximity to green-power corridors." Energy is capacity becomes the industry's new paradigm. Whoever locks in low-cost clean power locks in pricing power for the next generation.