DIGITIMES Insight: Intel, TSMC, Samsung converge on backside power — packaging becomes the next divide

When AI accelerator power crosses 4,000W, the power delivery network ceases to be infrastructure and becomes the binding constraint. Under frontside routing, I²R losses scale quadratically with current, starving the active region of over half of delivered energy. Backside power delivery is therefore not a process option—it is a physical imperative. The ripple effects extend far beyond packaging. Decoupling power from signal layers forces a redesign of GAA gate stacks, EUV layer budgets, and HBM TSV density. More critically, packaging elevates from a back-end step to an architectural decision layer. Power-integrity simulation will overtake timing closure as the dominant EDA workload, triggering a toolchain restructuring. The competitive race is fundamentally a yield sprint. Intel leverages PowerVia to reframe its foundry narrative from catching up to leading. TSMC, anchored by its CoWoS ecosystem and manufacturing scale, is positioned to ship backside-power-plus-3D-stacking in volume by 2026. Samsung bets on HBM vertical integration. All three converge on the same destination, but the execution window is only 18–24 months—miss it, and you lose the next-generation AI silicon ticket. The 12–24-month tail: power-network design capability will replace process node as the primary KPI for foundry selection; High-NA EUV procurement logic shifts from performance to power-layer precision; and packaging's share of total chip value migrates from roughly 15% toward 30%, redrawing the semiconductor value chain's power map.