DIGITIMES Insight: AI packaging power reaches kilowatt scale as thermal design moves toward the die

The kilowatt threshold marks a phase transition in packaging physics, not an incremental spec bump. TIM-less architecture elevates thermal management from interface engineering to bulk-phase engineering—microchannel liquid cooling embedded in the lid makes the cooling loop a first-order design variable in chip architecture. This forces CoWoS, Foveros, and competing advanced packaging to redefine thermal flux distribution at the interposer level. Jentech Precision is repositioning from component supplier to architectural co-designer, a fundamental shift in valuation logic. Risk: Phase-change materials and microchannel fabrication remain geographically concentrated in Taiwan, China and Japan, creating a new export-control sensitivity. Kilowatt-class packaging pushes single-rack power beyond 50 kW, externalizing EU ErP and US DOE compliance costs directly into chip architecture decisions. Competitive dynamics: NVIDIA and AMD will likely standardize microchannel liquid cooling in BOMs by 2026, forcing Boyd and Auras into an integrate-or-be-replaced binary. TIM incumbents like Dow and Henkel face structural share erosion within 18 months unless they build patent moats in phase-change materials. Within 18 months, thermal design becomes a hard gate for AI chip tape-out. Once the kilowatt threshold solidifies, air-cooled data centers accelerate their retirement and liquid-cooling infrastructure capex enters an exponential curve. Thermal management is no longer a cooling problem—it is the first-order constraint on AI compute density.