CXMT president says company’s first 4F² DRAM will be a server DDR5 RDIMM due by year-end

The strategic signal isn't the node number—it's the product choice. CXMT bypassing mobile LPDDR to debut in server DDR5 RDIMM is a deliberate play: wider timing margins during yield ramp, and an $8-12/GB price band sitting in the vacuum between Samsung's 1c and SK Hynix's 1β nodes. Technically, 4F² compresses cell area to roughly 60% of 6F², pushing trench aspect ratios and ALD uniformity close to EUV-grade tolerances. This creates a real qualification window for domestic equipment makers (NAURA, AMEC) in etch and deposition. The single point of failure remains DUV multi-patterning dependency on ASML NXT:1980 stock—any maintenance disruption in 2026 could stretch ramp cycles from 18 to 30+ months. Expected competitive response: Hynix pulls 1γ forward by 1-2 quarters to widen the generational gap; Samsung applies a 5-8% defensive price cut on existing DDR5 RDIMM. But the structural threat isn't price—it's the 12-24 month window where Inspur, H3C, and other server OEMs initiate second-source qualification. Passing that audit embeds CXMT directly into server BOMs, bypassing price competition entirely. Long-tail verdict: if 4F² validates at scale, it's an architectural leap, not a process catch-up. That rewrites the 'permanently one generation behind' narrative for China's DRAM industry.