Custom HBM Era Emerges with AI Chipmaker-Memory Collaboration - 조선일보

Custom HBM is fundamentally a reallocation of industrial power, not a product iteration. When chip designers penetrate into TSV stacking, micro-bump pitch, and substrate selection, the JEDEC standardization framework is being structurally bypassed — echoing how Intel's 2010s integration of memory controllers into CPUs shifted DDR influence from open consortiums to a single dominant buyer. Technically, custom HBM elevates CoWoS packaging from a back-end process to an architectural decision point. Co-optimizing bandwidth and latency demands that on-chip network topology be designed in lockstep with HBM bank mapping, raising the technical bar for EDA tooling and ABF substrates while structurally shifting bargaining power toward substrate suppliers. On supply-chain risk, HBM capacity remains heavily concentrated in Taiwan, China's packaging lines and South Korea's memory fabs. If U.S. export controls extend to HBM4 custom design data, non-aligned markets lose direct access to the technology stack, and compliance costs will escalate non-linearly. Competitively, Samsung is leveraging HBM3E qualification to capture custom orders, while Micron bets on a logic-based base die for HBM4 to leapfrog. The exclusivity of 2-to-3-year design cycles means late entrants face an irreversible structural window loss. Within 18 months, chip-memory co-design consortia will emerge as the dominant industry architecture, and packaging capacity scarcity will surpass wafer foundry as the true bottleneck in the AI compute race.