CPO delays may shift AI networking demand, not derail it

Yield issues in co-packaged optics (CPO) reveal a critical gap in co-design between advanced packaging and photonic integration, pushing AI chipmakers to temporarily fall back on pluggable optics—raising power and footprint costs for 800G/1.6T deployments. TSMC (Taiwan, China) and Intel are accelerating silicon photonics integration, while NVIDIA may leverage this delay to push its NVLink-C2C electrical interconnect standard. Tightening U.S. export controls on advanced packaging tools have indirectly raised validation barriers for non-U.S. foundries, deepening supply chain fragmentation. Over the next 18 months, a 'performance compromise window' will emerge: system vendors accept higher latency and energy use, creating breathing room for interim solutions like LPO (Linear-drive Pluggable Optics). Crucially, CPO delays won’t curb AI infrastructure scaling—they’ll accelerate ecosystem consolidation, with firms mastering chiplet-plus-optical-I/O co-integration poised to dominate next-gen AI hardware.