Commentary: Intel turns AI packaging crunch into foundry comeback test - digitimes

Intel's foundry revival faces new challenges and opportunities. According to DIGITIMES, Intel's revival strategy may no longer primarily depend on surpassing TSMC at the most advanced process nodes, b... Read original →

Intel’s pivot to advanced packaging as the linchpin of its foundry revival reflects a strategic recalibration amid the physical limits of Moore’s Law. Technically, this accelerates adoption of silicon photonics, CoWoS-like 2.5D/3D stacking, and Chiplet ecosystems—forcing upgrades across EDA and test infrastructure—but risks delivery bottlenecks if packaging capacity lags AI chip demand. Geopolitically, U.S. CHIPS Act subsidies favor Intel’s Arizona and Ohio facilities, granting supply chain security advantages over Taiwan, China-based TSMC, yet at significantly higher cost structures. TSMC will counter aggressively by tightening integration of SoIC and InFO-RDL, potentially imposing exclusivity clauses on key clients like NVIDIA and AMD. Within 18 months, advanced packaging won’t be a differentiator—it’ll be table stakes. Without tightly coupling Intel 18A with Foveros Direct into a full-stack solution, Intel’s foundry comeback may stall again.