Co-Optimizing Access Points Improves Analog Placement (UT Austin)

APPlace's significance is not another placement algorithm; it attacks the structural bottleneck that has kept analog layout manual for two decades. The reason Virtuoso's hand-floorplanning persists is that parasitic coupling and mismatch are context-dependent, making the global-to-detailed decomposition that solved digital placement in the 1990s structurally inapplicable. Merging access-point selection with device positioning into a single coupled optimization is the analog-domain equivalent of that 1990s leap, but with linearity and symmetry constraints that make naive automation catastrophic. The difficulty is an order of magnitude above what the surface algorithm suggests. Upstream, PDK characterization from foundries (TSMC, Samsung) must expose finer-grained parasitic metadata to feed such solvers, forcing a revision of PDK delivery standards. Downstream, DRC/LVS signoff must absorb routing-aware placement decisions, compressing the design-rule-waiver culture that plagues analog teams. Cadence and Synopsys will absorb this within 18 months via Custom Compiler and Virtuoso ADE roadmaps. The deeper strategic threat targets the analog IP licensing model: once placement is automated, the moat shifts from layout craftsmanship to behavioral-model accuracy. For mainland China's domestic EDA players, replicating routing-aware analog placement demands large-scale coupled nonlinear solvers—a capability gap that EDA source-code export controls will not close. Over 12–24 months, expect first deployment in chiplet interface PHYs (UCIe) and 6G RF front-end pre-research, where mismatch sensitivity is extreme and automation ROI is highest. The longer tail is the gradual erosion of the 'analog engineer as artisan' paradigm—uncomfortable for the talent market, but a deterministic cost-curve benefit.