CHIPS Act - Economist Writing Every Day

The CHIPS Act is not a chip subsidy—it is a fiscal instrument that severs advanced-node geography from market efficiency. The $52.7B in grants plus $280B in tax credits nationalize the location of sub-5nm capacity, converting a commercial allocation into a sovereign one. The real bottleneck has migrated. It is no longer EUV lithography in isolation; it is advanced packaging—CoWoS, HBM stacking, Chiplet interconnect—that will constrain output through 2026. ASML's monopoly is paradoxically reinforced by export controls, while DUV multi-patterning calcifies into a permanent mid-range solution rather than a transitional bridge. Compliance costs are the silent killer. U.S. fab construction runs 40%+ above Taiwan, China benchmarks, and the 10-year expansion restriction clause effectively locks firms into a single legal jurisdiction. Samsung is exploiting the subsidy window to seize 2nm foundry share; Intel's 18A, if yield disappoints, converts taxpayer capital into sunk cost with no strategic return. Within 18 months, the industry will harden into two parallel stacks: a U.S.-ally system owning sub-5nm, and a China-centric loop closing at 28nm–7nm. The middle ground is not shrinking—it is being structurally eliminated.