Chiplets: Panel Discussion: Scaling Chiplets Without Breaking the System – Where are the Limits?

Chiplet scaling is hitting a structural ceiling the industry has systematically underestimated. The bottleneck has migrated from lithography to the compounding constraints of packaging, interconnect, thermal, and system verification. UCIe standards are live, yet the bandwidth-latency-power triangle in 2.5D/3D stacks remains unsolved; each additional die layer compresses thermal design margin by roughly 15%. This is a physics ceiling, not an engineering optimization problem. Supply-chain concentration is the quiet risk. Advanced packaging capacity is bifurcated between TSMC's CoWoS lines in Taiwan, China and Intel's EMIB/Foveros. With export-control-driven equipment lead times stretching past 18 months, packaging is replacing lithography as the new strategic chokepoint. NVIDIA and AMD share the same packaging supplier; Intel's bid for an independent Foveros+EMIB ecosystem is lagging on yield ramp. Over the next 12-24 months, system-level verification costs will erode 30-40% of the cost advantage chiplets were supposed to deliver. 'Packaging as strategy' is moving from boardroom rhetoric to balance-sheet reality.