Chiplets: Panel Discussion: How Should We Reimagine the Design Flow for Chiplet Scalability

This panel exposed a structural contradiction far sharper than the surface debate: the entire EDA toolchain and IP reuse paradigm was architected for single-die SoCs. Forcing it onto heterogeneous multi-die integration is like applying horse-drawn carriage traffic rules to a highway. The real bottleneck isn't front-end RTL—it's physical verification, thermal management, and die-to-die signaling. In multi-vendor scenarios, PDKs, DRC rules, and timing constraints diverge per supplier, making sign-off convergence nearly impossible. If Synopsys and Cadence don't ship chiplet-native design environments by 2026, the ecosystem gets locked into Intel's Foveros or TSMC's CoWoS proprietary packaging flows. On compliance, multi-vendor chiplet assembly is a minefield under export controls. Each die's fabrication origin and IP provenance constitutes a separate review node. BIS de minimis rules effectively collapse under this architecture, driving compliance costs up exponentially. Strategically, AMD is betting on open UCIe to attract third-party suppliers, while Intel builds a closed vertical stack via EMIB. TSMC's CoWoS capacity is, in essence, a monopoly on the integration layer itself. Within 18 months, the "do we need fundamental change" question becomes moot. Two parallel tracks emerge: open-standard (UCIe plus open PDK) versus vertically integrated. Mid-tier fabless players will be forced to pick a side, accelerating industry consolidation.