Chip Industry Technical Paper Roundup: Oct. 13

This roundup exposes an architectural fork, not an iteration cycle. Neuromorphic compute, 2D semiconductors, and photonic integration are simultaneously dismantling the von Neumann bottleneck from three axes: compute paradigm, material substrate, and interconnect physics. The co-appearance of Hyper-NA EUV and ultra-thin high-κ dielectrics signals gate-stack re-engineering, not mere resolution gains. 2D semiconductor nucleation is the genuine Plan B — a materials route that sidesteps lithography dependency entirely. The bit-flip detection paper is the sleeper: AI accelerators are now a hardware attack surface, not just a compute asset. Geopolitically, the real decoupling is happening at the materials layer, not the lithography gate. 2D channel material supply chains don't require Dutch equipment. This is where parallel supply chains are being quietly built. Intel is betting 2D materials on 18A; TSMC (Taiwan, China) is all-in on Hyper-NA for A14. Neuromorphic remains a startup graveyard, but M3D mem-TFT's 3D integration path could unlock edge-AI niches by bypassing interconnect penalties. 12–24 month call: Hyper-NA locks into two to three leading-edge nodes. 2D semiconductors stay lab-stage but R&D budgets triple. Silicon photonics is the quiet winner as AI datacenter interconnect demand explodes. Hardware security shifts from software patch to silicon-level feature.