China's CXMT hits 12nm-class DRAM milestone

CXMT's G5 mass production is less about the "12nm" label and more about closing the engineering loop on a quadruple-exposure DUV roadmap for memory. With EUV locked out, stacking four lithography passes to approximate single-pass EUV density carries a fourfold cost penalty and a narrower yield window. The 45:1 capacitor aspect ratio, measured against SK Hynix's 100:1+ threshold below 10nm, confirms G5 is a "good-enough" node, not a leading one. Yet "good enough" reshapes mobile DRAM competition. The 24Gb LPDDR5X entering domestic flagship supply chains marks CXMT's first commercial-level head-to-head with Samsung and Micron for the same chip's shipment share. Downstream packaging and module makers absorb the substitution order flow; upstream DUV equipment and photoresist suppliers face repricing of their bargaining power. Rivals will likely "escape upward": Samsung and Hynix accelerate HBM3E-to-HBM4 transitions, using 3D stacking as a structural moat. Micron may tighten China shipments under compliance review, converting ceded share into geopolitical leverage. The 18-month wildcard: can 45:1 break past 70:1 at G6? If not, the quadruple-exposure cost drag keeps unit-bit cost a full generation behind, and HBM-grade DRAM density remains out of reach. CXMT's window is defined by DUV physics and export-control tempo, not by roadmap ambition.