China's AI chipmakers target 3D packaging, optical interconnects and software ecosystems

China's AI chip pivot from single-die performance to system-level integration is fundamentally a circumvention strategy against export controls, not a genuine architectural leap. The 3D packaging push immediately pressures the advanced substrate and thermal management supply chain—ABF carrier board capacity held by Japanese suppliers becomes the new chokepoint, while optical interconnects shift the bottleneck toward InP epitaxial wafers and modulator yield, areas where domestic self-sufficiency remains incomplete. The software ecosystem is the real temporal moat: a decade of CUDA operator libraries cannot be replicated through open-source alone. The pragmatic play is anchoring to PyTorch backends for 'good-enough' inference clusters. NVIDIA will likely accelerate CPO deployment and tighten CUDA licensing terms; AMD may expand ROCm compatibility to capture spillover demand. Within 12-24 months, Chinese AI clusters will cross the usability threshold on inference workloads, but training remains constrained by HBM bandwidth and packaging yield—producing a structural split: inference autonomy, training dependency.