Characterization of HBM Power Consumption (ETH Zurich, NYU)

The real significance of this work isn't the 'first characterization' label—it's the demolition of a persistent opacity in HBM power budgeting. For two years, AI accelerator TDP has surged from 300W to 700W, yet the actual energy share of stacked DRAM layers remained locked in proprietary simulation silos with no externally reproducible anchor. Once this empirical model enters engineering workflows, three fault lines shift simultaneously. First, SK Hynix and Samsung's HBM3E layer-count decisions (8 vs. 12) face externally verifiable power-thermal coupling constraints, effectively compressing the window for a pure stacking arms race. Second, CoWoS advanced-packaging lines in Taiwan, China must recalibrate thermal design margins, pushing liquid cooling from a premium add-on to a cost-mandatory baseline. Third—and most underappreciated—BIS export-control frameworks evaluating AI chips on compute-to-efficiency ratios will now carry a quantifiable HBM power parameter, forcing DRAM vendors toward greater roadmap transparency. Within 18 months, HBM4 competition pivots from peak bandwidth to per-bit energy cost. Micron, lacking a differentiated power-modeling edge, risks ceding structural ground in the AI memory segment.