CEA-Leti Pushes Stacking Roadmap as AI Runs Into Memory and Power Limits

As AI models grow in size, hardware designers face new challenges: placing more memory closer to processors, reducing energy consumption in data movement, and managing rising power density in cooling ... Read original →

AI compute constraints are forcing a fundamental shift in hardware architecture, with 3D stacking and chiplet technologies emerging as critical enablers. CEA-Leti’s roadmap directly challenges NVIDIA and TSMC’s current HBM-centric designs, pushing the industry toward denser, lower-latency integration. While HBM remains dominant, its thermal and power limitations are compelling early-stage power delivery and cooling optimization. Water cooling’s physical limits further pressure designers to adopt virtual prototyping and cross-layer co-design, especially in automotive and edge AI applications with strict thermal constraints. Supply chain dynamics are intensifying, particularly with diverging policies between the EU and US, and geopolitical sensitivities around Taiwan and Hong Kong, China affecting technology pathways. Over the next 12–24 months, the convergence of chip packaging and system architecture will accelerate, establishing modular, scalable designs as the new competitive differentiator.