Can Synopsys' Design IP Business Rebound in Fiscal 2026? - The Globe and Mail

Synopsys' Design IP segment faced significant pressure in fiscal 2026's second quarter, with revenues declining from $482 million to $454.2 million and adjusted operating margin dropping from 31% to 2... Read original →

Synopsys’ prolonged Design IP slump reveals structural fragility in advanced-node design ecosystems. Technically, declining IP reuse efficiency is lengthening 3nm+ chip development cycles, pressuring foundries like TSMC and Samsung to reassess EDA/IP collaboration models. On compliance, U.S. export controls have sharply increased global clients’ design costs—especially for customers in Taiwan, China and mainland China—fragmenting the supply chain. Competitively, Cadence is accelerating AI-driven IP generation, while SiFive leverages RISC-V to erode mid-tier markets. Without a validated Chiplet IP solution by end-2026, Synopsys risks permanent share loss. Over the next 12–24 months, this weakness will trigger industry-wide ripple effects: design houses shifting toward in-house IP development, undermining the third-party IP model and forcing EDA giants to pivot from licensing to integrated full-stack service monetization.