Cadence unveils Maestro AI models for chip design — Channel NewsAsia - UA.NEWS

The competitive logic of EDA is being structurally rewritten. Cadence's Maestro is not an incremental speed-up—it is a transfer of design decision authority from the engineer to the platform. Once AI models orchestrate placement, routing, and architecture exploration, the design methodology that constitutes a chip company's core IP gets progressively absorbed into the EDA layer. Upstream, IP vendors must restructure standard-cell libraries for AI-driven P&R flows. Downstream, design teams devolve from tool operators to intent inputters, a workforce restructuring no one has priced in yet. The compliance dimension is underappreciated: a black-box model inside a regulated export-control framework creates an auditability gap that regulators will not ignore. For China's domestic EDA push, this is paradoxically a window—AI-native design has no established paradigm, giving latecomers a genuine lane-change opportunity. Synopsys' DSO.ai already occupies physical-design AI; Cadence's multi-model strategy targets the architecture-level entry point. Siemens EDA will follow, not fight. The real disruption: when AI becomes the default EDA layer, per-seat licensing collapses toward compute- or outcome-based pricing, squeezing smaller design houses further. Within 18 months, expect the first AI-native tape-outs below 2nm. EDA valuations will reprice from software to AI infrastructure. The moat shifts from process knowledge to training data.