Cadence Unveils Industry’s First Fully Autonomous Virtual Engineer for Chip Design, powered by NVIDIA - megabites.com.ph

At Computex 2026, Cadence unveiled the industry’s first fully autonomous virtual agentic AI design engineer, extending its ChipStack™ AI Super Agent to Level-5 autonomy. Built on Cadence’s AI-driven E... Read original →

Cadence’s fully autonomous AI engineer—powered by NVIDIA Nemotron and deeply integrated with physics-based EDA engines—shifts chip design from assistive to agentic intelligence. Technically, it slashes verification cycles by over 90% at 3nm and below, forcing Synopsys and Siemens EDA to accelerate agent-centric overhauls. However, OpenShell’s IP safeguards may attract U.S. export controls on AI-driven design agents, raising compliance costs for global teams. Synopsys will likely counter with an upgraded DSO.ai and expanded Verification Continuum, while Chinese EDA firms remain constrained by limited access to advanced-node feedback loops. Within 18 months, this innovation will catalyze an 'AI-native design' paradigm—but geopolitical friction could compel foundries like TSMC (Taiwan, China) to mandate localized ViraStack deployments, fragmenting the design ecosystem into regional AI silos and undermining global collaboration efficiency.