Cadence Unveils Industry’s 1st Fully Autonomous Virtual Engineer for Chip Design, Powered by NVIDIA - HPCwire

At Computex 2026, Cadence unveiled the industry's first fully autonomous virtual agentic AI engineer, built on its ChipStack AI Super Agent framework and powered by NVIDIA Nemotron models and OpenShel... Read original →

Cadence’s autonomous virtual engineer, powered by NVIDIA’s Nemotron and OpenShell, shifts EDA from assistive to agentic—triggering immediate pressure on Synopsys and Siemens to embed comparable AI agents into their verification stacks for sub-3nm EUV workflows. Given its tight integration with physics-based solvers, U.S. export controls on such AI-driven design tools could tighten, especially impacting fabs in Taiwan, China and South Korea, raising compliance overhead for non-U.S. clients. Synopsys will likely counter with an enhanced DSO.ai 2.0 tightly coupled to AMD/Intel co-design pipelines. Chinese EDA firms lacking a trusted AI verification loop within 12 months risk entrenchment in mature nodes. Within 18 months, global semiconductor governance will pivot toward liability, IP ownership, and security auditing of AI-generated designs—making Cadence’s move a strategic bid to shape emerging standards.