Cadence introduces autonomous AI engineer for chip design workflows - New Electronics

Cadence Design Systems has introduced a new autonomous artificial intelligence (AI) system aimed at transforming semiconductor design workflows. This marks the industry’s first virtual agent capable o... Read original →

Cadence’s autonomous AI engineer, powered by NVIDIA Nemotron and OpenShell, signals a paradigm shift from AI-assisted to AI-autonomous chip design. Technically, its Level-5 autonomy forces a redesign of verification IP, testbench generation, and even EUV OPC flows for sub-3nm nodes. Geopolitically, the tight integration within a U.S.-controlled secure runtime heightens access barriers for fabs in mainland China and Taiwan, China. Competitors like Synopsys will likely fast-track generative AI agents and open partial AgentStack APIs to retain ecosystem relevance. Within 18 months, this will catalyze demand for 'AI-native architects' and compel foundries to embed AI co-verification infrastructure—or risk losing competitiveness at advanced nodes.