Cadence expands Intel Foundry collaboration on chip design By Investing.com - Investing.com India

Cadence's expanded collaboration with Intel Foundry represents a significant development in the semiconductor industry, highlighting the growing importance of strategic partnerships between EDA tool p... Read original →

Cadence’s deeper integration with Intel Foundry is a strategic response to the growing design-manufacturing misalignment below 3nm. Tight coupling of EDA flows with foundry PDKs and yield models can cut AI/5G chip iteration cycles by at least 20%, directly challenging the Synopsys–TSMC (Taiwan, China) ecosystem dominance. Geopolitically, U.S. CHIPS Act mandates for domestic production compel EDA vendors to anchor to American foundries to satisfy subsidy compliance, raising integration costs for non-U.S. supply chains. Equipment makers like ASML may soon be pulled into joint validation loops, extending lead times. Within 18 months, such design-manufacturing alliances will become industry norms—but will also lock out smaller IC designers lacking access to these closed-loop platforms, effectively barring them from advanced-node tapeouts.