Cadence expands Intel Foundry collaboration on chip design By Investing.com - Investing.com Australia

Cadence's expanded collaboration with Intel Foundry represents a significant advancement in semiconductor industry partnerships, particularly for advanced process technology development. This strategi... Read original →

Cadence’s deepened 3nm collaboration with Intel Foundry marks a strategic vertical integration of EDA toolchains and advanced manufacturing. Technically, it pressures Synopsys to accelerate Fusion Compiler co-optimization with TSMC’s A16/A14 nodes and pulls ASML’s EUV into earlier design validation cycles. On compliance, tightening U.S. export controls raise licensing costs and delivery risks for Chinese clients, especially in AI chips. Competitively, TSMC may reinforce its ecosystem via tighter Synopsys/Ansys joint certifications, while Samsung could lure North American designers with aggressive IP-sharing terms. Over the next 12–24 months, such design-manufacturing closed-loop alliances will become industry norms—but at the cost of fragmenting the global supply chain, as non-U.S. foundries face higher barriers to accessing cutting-edge EDA support.