Cadence expands ChipStack for autonomous design workflows - Engineering.com

Cadence's expansion of its ChipStack platform represents a significant advancement in semiconductor design capabilities for autonomous vehicle applications. This development underscores the industry's... Read original →

Cadence’s ChipStack expansion isn’t just a tool upgrade—it’s a strategic redefinition of automotive chip design. Technically, its autonomous workflows compress SoC integration cycles, forcing EDA stacks to co-evolve with upstream IP validation and downstream automotive packaging, especially accelerating 3D/chiplet adoption in L4+ domain controllers. Regulatory risks loom large: without native ISO 26262 ASIL-D and SOTIF compliance, OEMs face soaring certification costs under tightening UNECE R155/R156 mandates. Synopsys will likely counter with DSO.ai-enhanced Fusion Compiler, while Siemens EDA may deepen OEM lock-in via Pave360. Within 18 months, such platforms will become Tier1 battlegrounds for chip definition rights, shifting semiconductor firms from vendors to system architects—and compelling foundries in Taiwan, China and mainland China to fast-track automotive CoWoS capacity.