Cadence deepens Intel Foundry partnership on next-generation chip design - digitimes

Cadence and Intel Foundry have expanded their strategic partnership in next-generation chip design, a move that could significantly impact semiconductors used in devices and data centers globally. Thi... Read original →

The Cadence–Intel Foundry alliance reflects an industry inflection point where EDA and foundry co-optimization is no longer optional but essential for sub-2nm design viability. This integration directly accelerates power-performance targets for AI accelerators and 5G infrastructure, forcing rivals like Synopsys to deepen their own foundry-specific flows. Geopolitically, tighter U.S. export controls on advanced compute chips mean any collaboration involving Taiwan, China or Korean fabs faces heightened licensing scrutiny, inflating supply chain risk. In response, TSMC will likely fast-track its Synopsys-powered 3DFabric ecosystem, while Samsung leverages HBM3E yield gains to poach AI clients. Over the next 18 months, such vertical partnerships will become table stakes—but the real differentiator lies in early dominance of chiplet-based heterogeneous integration and photonic I/O. Intel’s foundry ambitions only gain teeth if this tie-up narrows the volume-production gap with TSMC’s N2 node.