Cadence and Samsung Foundry Deepen 2nm and 3D‑IC Collaboration - HPCwire

Cadence's deepening collaboration with Samsung Foundry in 2nm advanced process and 3D integrated circuit technologies represents a significant advancement in semiconductor manufacturing capabilities. ... Read original →

The deepened Cadence–Samsung Foundry alliance on 2nm and 3D-IC will trigger cascading upgrades across EDA, advanced packaging, and materials. TSMC’s tighter IP control over its 3D stacking interfaces limits alternatives, pushing HPC clients toward strategic dependency. Persistent U.S. export controls on High-NA EUV tools risk delaying Samsung’s 2nm ramp, inflating Cadence’s validation overhead. In response, Synopsys will likely accelerate co-optimization with TSMC’s 3DFabric and double down on AI-enhanced signoff flows. Within 18 months, this partnership will force Chiplet adoption from optional to essential—especially within tightly coupled tech corridors spanning Taiwan, China; Korea; and the U.S.—marginalizing foundries lacking heterogeneous integration capabilities.