Broadcom executive says chipmakers must tackle packaging, power limits together

The AI compute density wall has fundamentally shifted the bottleneck from transistor scaling to system-level integration. Ostojic's remarks are an admission that process nodes alone cannot sustain next-gen accelerators—packaging, PDN, and thermal management must be redefined as a "second Moore's Law." Technical cascade: Once a single AI die exceeds 5,000 mm², 2.5D/3D packaging becomes the only viable path. Surging current density forces PDN redesign from chip-level to board-level, and thermal solutions must jump from air to liquid or immersion cooling. ABF substrates, glass core, and 800V DC delivery must iterate in lockstep—a single lagging link becomes the system's weakest point. Supply-chain exposure: Advanced packaging equipment (hybrid bonding, inspection) now sits under export controls, while CoWoS capacity remains heavily concentrated at TSMC in Taiwan, China. Geopolitical risk is being priced directly into capacity premiums. Data-center power permitting cycles are lengthening, adding hidden costs. Competitive dynamics: Broadcom's messaging signals to NVIDIA and custom-ASIC clients that system-level co-design is the new moat, while legitimizing Intel's EMIB and Samsung's I-Cube as credible alternatives. UCIe standardization is eroding any single packaging vendor's pricing power. 12–24 month outlook: Liquid cooling becomes default, glass substrates enter production validation, and 800V architectures land in hyperscale data centers. The competitive axis shifts from "who has the leading node" to "who integrates the system most efficiently."