Bringing Down Test Costs For Co-Packaged Optics

The real bottleneck in CPO mass production isn't photonic PDK maturity—it's the irreversible test economics post-packaging. Once silicon photonics are physically fused with GPU/HBM in 3D stacks, the traditional test-reject-repackage yield paradigm collapses. A 200nm coupling deviation is a scrap mark pre-packaging; post-packaging, it's a $3,000+ ASIC module written off. This is the true killer in CPO's cost curve. Structurally, the test bottleneck is rewriting supply-chain division of labor. If TSMC's COUPE platform cannot deliver complete optical KGD data before bonding, downstream OSATs absorb uncontrollable yield risk. Advantest and Teradyne face a generational shift: polarization state, thermal drift, and S-parameter characterization of photonic devices bear no resemblance to pure electrical test flows. This is a methodology reset, not "adding a station." Competitively, the Broadcom-NVIDIA CPO rivalry is fundamentally a contest over who owns the test-yield closed loop. If Marvell compresses test cost to under 1.5× pluggable optics at the 1.6T node, 2026 AI switch silicon share gets redistributed. The 12-24 month signal to watch: capex on wafer-level photonic test equipment. If GlobalFoundries and IMEC scale front-end optical engine test lines in H2 2025, industry consensus has crystallized—KGD must be solved at the die level. Only then does CPO's BOM cost inflection point actually arrive.