Industry Analysis
The ASML–SK Hynix revenue divergence is not cyclical noise; it is the physical signature of two opposing constraints in the AI compute stack: supply rigidity versus demand elasticity.
ASML's EUV delivery cycle (18–24 months) hard-caps accelerator front-end capacity. The 30% immersion expansion and photomask partnerships are buffer plays ahead of High-NA volume production. SK Hynix's HBM scaling, routed through TSV and hybrid bonding, carries far greater supply elasticity. When HBM4 compresses co-design cycles with logic dies to under 12 months, the two curves converge earlier than consensus models assume.
Risk dimension: ASML's export-control exposure is a structural cost multiplier—every tightening cycle reshuffles its customer mix. SK Hynix's Nasdaq ADR push and C-suite turnover are capital-access hedges against antitrust litigation windows, not organic growth signals.
Competitive dynamics: Samsung's HBM3E yield catch-up and Micron's HBM4 pre-qualification will compress HBM pricing power within 12 months, shifting the market from seller's to competitive equilibrium. ASML faces the inverse risk—High-NA validation delays at TSMC and Intel could force 2026 guidance cuts.
18-month outlook: the scissors gap narrows. HBM volume erodes memory margins; High-NA scarcity re-prices equipment premiums. The deeper structural shift: once 2.5D/3D packaging becomes the AI chip default, the lithography-memory boundary dissolves. "Complementary" becomes "co-designed," and value allocation across the chain resets.
This page displays AI-generated summaries and metadata for research purposes. Original content belongs to the respective publishers.