ASML, TSMC, and imec move 2D transistors closer to manufacturing reality

The successful integration of n- and p-type 2D transistors on 300mm wafers at 50nm contacted poly pitch by ASML, TSMC (Taiwan, China), and imec marks a pivotal shift from lab curiosity to manufacturable reality. This breakthrough pressures EUV tooling, ALD processes, and metrology systems to rapidly adapt to van der Waals channel materials. Geopolitically, reliance on ASML’s high-end lithography exposes non-U.S. foundries to export controls, inflating compliance overhead. Samsung and Intel will likely accelerate their own 2D roadmaps—Samsung may leverage its GAA infrastructure for narrative dominance. Over the next 18 months, patent battles over contact resistance and thermal stability will intensify, but wafer-scale uniformity remains the true bottleneck determining whether 2D transistors scale beyond niche applications or genuinely succeed silicon CMOS.