ASML eyes hybrid bonding, report finds, as Chinese firms adopt chip technique - South China Morning Post

Hybrid bonding is not a packaging upgrade—it is an architectural bypass around the EUV lithography chokehold. With export constraints capping Chinese node progression near 7nm, vertical stacking via sub-micron die-to-die interconnect becomes the only viable performance leap. You are essentially buying next-gen compute gains through packaging rather than photolithography. ASML's interest exposes a strategic paradox: its core moat is being eroded by its own customers' architectural choices. If chiplet-plus-bonding delivers 80% of the performance at 30% of the cost, the lithography value anchor shifts structurally downward. Upstream, alignment precision demands compress below 100nm, spawning an entirely new metrology and inspection toolchain. Downstream, HBM4, AI accelerators, and data-center processors all hinge on this path. China's packaging ecosystem—JCET, Tongfu, and fabless designers—is scaling faster than most Western models projected. Competitively, TSMC's SoIC, Samsung's X-Cube, and Intel's Foveros are racing in parallel. ASML's likely entry vector is acquisition of a bonding-equipment specialist (Besi or a Japanese player), not organic R&D. 12-to-24-month call: bonding throughput, not lithography capacity, becomes the true bottleneck in the AI compute supply chain. Whoever controls bonding yield controls the delivery cadence of next-generation compute architectures.