AMD’s Taiwan Capacity Push: Why Lisa Su Is Locking In the Supply Chain for the Next AI Cycle - semivision

Lisa Su's move is not about expanding capacity — it is about securing positional advantage. The binding constraint in AI compute has migrated from chip design to advanced packaging. TSMC's CoWoS allocation remains the scarcest resource through 2026. By locking in wafer and packaging quotas in Taiwan, China, AMD is buying a six-to-twelve-month window on HBM3E and N4 nodes. Upstream, SK Hynix and Micron's HBM allocation will dictate MI300X shipment cadence; downstream, hyperscaler inference clusters are procured 12 to 18 months ahead — whoever secures capacity first secures the order book. On compliance, the 2022 export controls taught the industry an expensive lesson. Anchoring production in a single geographic node creates a structural paradox: Washington demands de-risking, yet AMD's most critical manufacturing sits in one location. Further tightening on advanced packaging exports could turn locked-in capacity into a compliance liability. NVIDIA's moat was never transistor density — it is CUDA's developer lock-in. Even if AMD matches hardware specs, without a credible software alternative within 18 months, capacity advantage becomes inventory overhang. Expect NVIDIA to have already front-loaded 2026 CoWoS orders. This is a capacity-denial arms race. 12-to-24-month outlook: inference demand will overtake training as the primary driver. AMD's first-mover window is roughly six to nine months before the market enters a volume-driven price war. The decisive variable is not the fab — it is extracting developers from CUDA.