AMD's Lisa Su says memory is becoming another pressure point for AI chips

Memory is transitioning from a supporting component to a critical bottleneck in AI accelerators, reshaping compute architectures beyond packaging constraints like CoWoS. HBM bandwidth and capacity now directly dictate large model training throughput, yet supply is concentrated in just three players—SK Hynix, Samsung, and Micron—amplifying geopolitical exposure, especially as U.S. export controls extend to HBM3E. While AMD secures adequate CoWoS capacity from TSMC, its MI300 series risks competitive disadvantage against NVIDIA’s H100/B100 without long-term HBM commitments. NVIDIA has already locked in SK Hynix output via multi-billion-dollar prepayments. AMD may be forced to accelerate proprietary chiplet memory interfaces or invest in onshore alternatives. Within 18 months, HBM access will become the second front in the AI chip war, sidelining vendors lacking vertical integration.