AI squeezes chip component capacity as Zyxel flags longer lead times, higher memory costs

The AI infrastructure buildout is rewriting pricing rules for non-AI semiconductors. Zyxel's 11.4% QoQ revenue decline is not an isolated data point—it is the structural consequence of wafer capacity being systematically cannibalized by HBM, CoWoS advanced packaging, and AI accelerators. When fabs pivot toward high-margin AI products, supply elasticity for DDR buffer memory, Ethernet PHYs, and SerDes chips used in network equipment gets compressed. This is reallocation, not a cyclical blip. On supply chain risk, Zyxel lacks Cisco's bargaining depth or Huawei's vertical integration. Squeezed between surging memory prices and telecom capex contraction, margins face bidirectional pressure. Lead times stretching from 8 to 20+ weeks break the inventory models of mid-tier equipment makers, forcing passive high-price lock-in strategies. In competitive dynamics, Arista benefits from the same capacity tilt by being AI-datacenter-adjacent; Cisco secures supply via long-term agreements; Zyxel's SMB niche faces brutal price wars or must pivot toward SDN to offset hardware costs. 12-24 month call: AI's capacity gravity will not fade. Non-AI chip premiums stay elevated through 2027. The network equipment sector will see mid-tier players exit, and the "AI tax" becomes a permanent hidden cost embedded in the mature-node ecosystem.