‘AI is reshaping how chips are designed, built, and optimized’: Sudeep Shivalli, Regional Sales Director, GTM, Synopsys India - APAC Media

In the era of rapid AI advancement, the semiconductor industry is undergoing a fundamental transformation in how chips are designed, manufactured, and optimized. Sudeep Shivalli, Regional Sales Direct... Read original →

AI-driven chip design is triggering a deep-stack reconfiguration: upstream, generative AI compresses RTL-to-GDSII cycles, forcing EDA tools to evolve from automation to intelligent decision-making; downstream, sub-3nm nodes and chiplet architectures intensify demands on EUV yield and advanced packaging, compelling tighter design-manufacturing data loops. India’s ‘Atmanirbhar Bharat’ push accelerates local IP ecosystems but heightens supply chain fragility due to reliance on U.S.-based EDA platforms like Synopsys—especially amid tightening U.S. tech controls. Cadence and Siemens EDA will likely counter by acquiring AI optimization startups and promoting open standards to erode Synopsys’ ecosystem lock-in. Over the next 18 months, performance leadership will shift from transistor density to system-level hardware-software co-design, marginalizing players lacking integrated AI-native stacks.