AI hands foundries pricing power: TSMC leads, but the boom spreads industry-wide

The AI chip demand surge—extending beyond GPUs to ASICs, PMICs, and networking ICs—is fundamentally rewriting foundry economics. Mature-node 8-inch fabs, once deemed legacy, now command pricing power due to constrained capacity for analog and power chips. TSMC leverages its CoWoS and HBM packaging moat to lock in premium clients, yet peers like UMC and Vanguard in Taiwan, China are strategically repositioning portfolios to capture margin uplift. Geopolitical friction intensifies: U.S. CHIPS Act subsidies mandate local investment, compelling foundries to build costlier, less efficient fabs in Japan and Mexico. Over the next 12–24 months, advanced packaging—not wafer supply—will emerge as the critical bottleneck, pushing hyperscalers toward pre-committing capacity or co-investing in dedicated lines. This isn’t a cyclical upswing; it’s a sovereignty-driven structural realignment of semiconductor value chains.