Weekly news roundup: From October 12 to October 18, 2026

Advanced packaging is quietly becoming the new node war. Tata's Dholera fab isn't suffering a yield crisis; it's trapped in a structural three-to-five-year customer qualification cycle that no capex can compress. This is the hidden tax on greenfield fabs in emerging markets: the physics of process validation does not bend to shareholder timelines. Intel's pivot toward Foveros and EMIB is a candid concession that the leading-edge logic window has closed. By weaponizing interconnect density and heterogeneous integration, Intel is building a moat where it can no longer win on transistor shrink alone. This mirrors TSMC's 2018-to-2020 strategic logic: when you cannot out-lithograph, you out-package. The more consequential signal is Micron and TSMC jointly scaling AI capacity in Taiwan, China and Japan. This reveals the true binding constraint on AI inference at scale: not GPU silicon, but HBM stacking and CoWoS throughput. Over the next twelve to twenty-four months, allocation of packaging capacity will dictate AI infrastructure pricing power. Whoever controls CoWoS and HBM quotas controls leverage over hyperscaler capex. Tata's Dholera project, absent repeatable qualified production by 2027, risks becoming an expensive capacity option rather than a structural player.