CXL-Connected MRAM Address AI Storage Latency

Everspin isn't selling another memory chip — it's proposing a new architectural stratum that breaks the two-decade DRAM/NAND binary. In AI inference, model weights no longer need cold-start loads from SSD; a persistent, DRAM-speed tier between them cuts latency by an order of magnitude. The ripple effect is immediate. CXL switch silicon (Astera Labs, Marvell) now faces heterogeneous memory nodes, doubling controller complexity. Downstream, inference accelerators must redesign memory scheduling, OS page-table management, and NUMA topology around a third tier. The real contest is against Samsung, SK Hynix, and Micron, all pushing CXL-attached DRAM with the narrative of extending DRAM's reach. Everspin undercuts that pitch: if 4GB scales to 64GB at competitive cost, DRAM's quasi-persistent value proposition erodes. But the weakness is structural — MRAM fab capacity is concentrated, 4GB is two orders of magnitude short of datacenter demand, and there's no HBM-class bandwidth story. The 18-month inflection: once CXL 3.1 lands, whether hyperscalers slot this into inference-cluster BOMs. A single AWS or Azure pilot in H2 2025 re-rates Everspin from niche storage to AI infrastructure. Without that, and with MRAM cost-per-GB stuck above 1.5× DRAM, this tier stays a white-paper exercise.