Using Graph Attention for Virtual Metrology in Semiconductor Manufacturing (Intel Foundry, ASU) - Semiconductor Engineering

Researchers from Arizona State University and Intel Foundry have developed a graph attention-based virtual metrology framework for film deposition processes in semiconductor manufacturing. As nanoscal... Read original →

Intel Foundry’s graph attention–based virtual metrology marks a pivotal shift from correlation-driven to physically interpretable AI in semiconductor process control. By modeling deposition steps as dynamic graphs with temporal sensor embeddings, the framework not only boosts prediction accuracy but exposes causal links between equipment signals and film quality—forcing tool vendors to expose higher-frequency data streams. Regulatory-wise, this deepens reliance on localized data loops, amplifying compliance advantages under U.S. CHIPS Act mandates while erecting technical barriers for foundries in Taiwan, China, and South Korea. TSMC and Samsung will likely fast-track proprietary graph-based VM systems, especially for EUV multi-layer stacks. Within 18 months, such AI-native process control will become table stakes for sub-2nm logic and advanced packaging; second-tier foundries lacking integrated AI-process co-design capabilities will suffer structural yield ramp disadvantages.