Fixing AI’s Bottlenecks: Memory, Scale, and Sparsity

At the 'Atoms to Bits: The AlphaBet of Intelligence v2.0' conference held in February 2026 at the University of Manchester, a panel discussion on neuromorphic engineering and physical computing delved... Read original →

The Manchester conference marks a pivotal shift: AI hardware is moving beyond brute-force scaling toward precision architecture. The memory bottleneck now eclipses transistor density, accelerating commercialization of 3D XPoint and nanowire-based devices. EUV and 3nm processes must co-evolve with memory-centric designs rather than just logic scaling. NVIDIA’s reliance on HBM for KV cache risks obsolescence in sparse computing regimes, while Intel and Micron could leapfrog via neuromorphic edge chips. Geopolitical pressure for AI hardware localization will inflate TSMC’s advanced packaging costs. Within 18 months, in-memory compute ASICs will become critical infrastructure for large models, enabling Google DeepMind and IBM to monetize architectural IP—potentially redrawing the AI chip competitive map.